| 摘要 |
PROBLEM TO BE SOLVED: To reduce the numbers of input-output pins and signal lines. SOLUTION: One of six parallel-serial conversion circuits 51 synchronizes a parallel composite signal CMP-P with 8-bit width inputted in 13.5 MHz frequency with a bit clock B-CLK outputted by a data clock output circuit 52 and converts it into a serial composite CMP-S. The frequency of the clock B-CLK is multiplied to eight times as high as 13.5 MHz. A DA conversion circuit 70a converts the signal CMP-S into an analog signal at every 8-bit word. The circuit 70a accurately recognizes the value of every word from continuous signals CMP-S without a pause on the basis of 13.5 MHz data clock D-CLK supplied by a data clock output circuit 53. |
