| 摘要 |
PURPOSE: A semiconductor device with high speed address decoder is provided to expedite the word line selection process between the point where external master signal is activated and the point where word line enable signal is enabled. CONSTITUTION: A semiconductor device with high speed address decoder is composed of decoding, responding, activating, and selecting. Low free decoder(31) pre-decodes low address(RAi) and latches pre-decoded low address during low address strobe signal's inactive state, more specifically internal master signal's(PR) inactive state. Internal signal generator(33) responds to active low address strobe signal and activates internal master signal into 'high' logic. Internal signal generator responds to activated low address strobe signal and activates enable signal(PNBLS) into 'high' logic, regardless of PR. Low main decoder(35) responds to active enable signal, decodes the free decoded low address(DRAij), and activates world line enable signal(NWEi) into 'high' logic. When NWEi is activated, corresponding word line is selected, activated, and the memory cell that corresponds to memory cell array(37) is selected.
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