| 摘要 |
A variable time delay network (210) includes segments (270, 260) which are connected in parallel to form variable time delay network (210). Segment (270) includes a varactor diode (222) and an inductive element (223) connected in series at an anode electrode (290) of varactor (222). A cathode electrode (291) of varactor diode (222) connected to a node (220). Segment (260) includes a varactor (221) and a bypass capacitor (224) connected in series at a cathode electrode (292) of varactor (221). Cathode electrode (292) is connected at a node (225). An anode electrode (293) of varactor (221) connected to node (220). The impedance at node (220) presented to a signal that is to be time delayed remains constant at the center frequency of the signal via a bias voltage applied at node (225) while controlling and changing the time delay of the signal via a bias voltage applied at node (220).
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