发明名称 A/D CONVERTER TEST SYSTEM AND METHOD
摘要 PROBLEM TO BE SOLVED: To provide A/D converter test system and method for substantially shortening test time by reducing the number of times of comparison required for analog/digital conversion. SOLUTION: This system is provided with an upper limit register 20 and a lower limit register 22 for storing respectively an upper limit value (x+m) and a lower limit value (x-m) from the expected value x and allowable range m of an externally inputted external input analog voltage, an A/D controller 24 for transmitting the upper limit value (x+m) and the lower limit value (x-m) and informing the compared result of the external analog input voltage, an SAR 26 for writing the upper limit value (x+m) and the lower limit value (x-m) therein, a digital/analog converter 28 for converting the upper limit value (x+m) and the lower limit value (x-m) written in the SAR 26 to an analog voltage and a comparator 30 for comparing the analog voltage with the external analog input voltage and informing the A/D controller 24 of the compared result.
申请公布号 JP2000209089(A) 申请公布日期 2000.07.28
申请号 JP19990007405 申请日期 1999.01.14
申请人 NEC CORP 发明人 TANAKA YOSHIKAZU
分类号 H03M1/10;(IPC1-7):H03M1/10 主分类号 H03M1/10
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