发明名称 WAFER-LEVEL PACKAGE AND METHOD OF MANUFACTURING THEREOF
摘要 <p>PURPOSE: A wafer-level package and method of manufacturing thereof is provided to improve manufacturing efficiency and to reduce manufacturing costs. CONSTITUTION: A wafer-level package(10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K, 10L, 10M, 10N) includes a semiconductor wafer(11) having at least one semiconductor chip circuit forming region(12) each including a semiconductor chip circuit each provided with test chip terminals(13B), at least one external connection terminal(14), at least one redistribution trace(15) provided on the semiconductor wafer(11), at least one testing member(16, 27, 33, 36), and an insulating material (17, 19, 20). A first end of the redistribution trace(15) is connected to one of the test chip terminals(13A) and the second end of the redistribution trace(15) is extended out to a position offset from the chip terminals(13, 13A, 13B). The testing member(16, 27, 33, 36) is provided in an outer region(18) of the semiconductor chip circuit forming region(12), and the second end of the redistribution trace(15) is connected to the testing member(16, 27, 33, 36)</p>
申请公布号 KR20000047931(A) 申请公布日期 2000.07.25
申请号 KR19990055091 申请日期 1999.12.06
申请人 FUJITSU LIMITIED 发明人 MARUYAMA SHIGEYUKI
分类号 H01L23/52;H01L21/301;H01L21/3205;H01L21/66;H01L21/82;H01L21/822;H01L23/58;H01L27/04;(IPC1-7):H01L23/52 主分类号 H01L23/52
代理机构 代理人
主权项
地址
您可能感兴趣的专利