| 摘要 |
PROBLEM TO BE SOLVED: To minimize phase jump in the clock switching in the case of selecting one of plural reference clocks, and synchronizing by a PLL circuit. SOLUTION: When a reference clock REF1 is selected by a selector 1, a selector 8 selects an input A, and a selector 9 selects an input B. A flip flop 6 frequency-divides the REF1 by 1/2, and a flip flop 7 executes the punching operation of a PLL output from an inverting circuit 11 by a reference clock FET2. When the REF1 is switched to the REF2 according to a selection signal CONT, the selectors 8 and 9 switch inputs A and B by a decoder 10. Phase jump is generated in the output of the selector 1, and when the phase of the flip flop 7 is obtained as a frequency-division phase which is made the closest to the phase of the flip flop 6 so that the phase jump can be minimized. |
