发明名称 |
Data processor and data processing system having two translation lookaside buffers |
摘要 |
A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.
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申请公布号 |
US6092172(A) |
申请公布日期 |
2000.07.18 |
申请号 |
US19970950668 |
申请日期 |
1997.10.15 |
申请人 |
HITACHI, LTD. |
发明人 |
NISHIMOTO, JUNICHI;NISHII, OSAMU;ARAKAWA, FUMIO;NARITA, SUSUMU;ITO, MASAYUKI;TODA, MAKOTO;UCHIYAMA, KUNIO |
分类号 |
G06F12/10;(IPC1-7):G06F12/00;G06F13/00 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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