发明名称 ASYNCHRONOUS VARIABLE LENGTH DECODING APPARATUS
摘要 PURPOSE: An asynchronous variable length decoding apparatus is provided to have a rapid processing speed, a less hardware area and a less power consumption by connecting plural logic operations in a domino logic and by making a finally selected thing be processed by a simplified programmable logic array(PLA). CONSTITUTION: An asynchronous variable length decoding apparatus comprises a mode sensing part(11) which receives a decoding request event signal(bsq_req) and a mode signal to invoke one of paths of a dynamic domino connection part(12). The dynamic domino connection part(12) is operated to use one path of the paths detected by the mode sensing part(11). A programmable logic array(PLA) part(13) processes a code from a second barrel shifter(17) to transfer a process completion signal, a symbol signal and a match signal as a process result to a bit stream decoder, and to transfer a code length and a calculation completion signal(c1) to an accumulation part(14) and the second barrel shifter(17). The code length accumulation part(14) receives the calculation completion signal and the code length to accumulate the code length, and transfers a shift length and a process completion signal(c3) to a first barrel shifter(16). A bit stream buffer part(15) receives a read signal fro the code length accumulation part(14) for reading a bit stream from a channel buffer, and transfers buffering bits to the first barrel shifter(16).
申请公布号 KR20000045108(A) 申请公布日期 2000.07.15
申请号 KR19980061636 申请日期 1998.12.30
申请人 KOREA TELECOM 发明人 KIM, GYUN SU;KO, JONG SEOK;KIM, SHI JUNG
分类号 H03M7/40;(IPC1-7):H03M7/40 主分类号 H03M7/40
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