BACK ANNOTATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To decrease pseudo timing violation at the time of timing verification by reducing the error between the circuit simulation result and cell delay information for logic simulation. SOLUTION: Based on the error between the circuit simulation result 1012 and cell delay information 1013 of gate level calculated by the approximate function thereof, delay error correction information 1015 depending on the input signal waveform rounding and output load capacity of a cell is calculated. While referring to the said delay error correction information 1015 from the input signal waveform rounding and output load capacity found at the time of delay value calculation for back annotation using layout information 1014, a delay value for back annotation is corrected.