发明名称 |
Read/write timing for maximum utilization of bidirectional read/write bus |
摘要 |
A method and apparatus for optimizing the efficiency of a data bus for a memory device. Extra latency is added between the time a memory controller issues a write instruction and the time the data is transferred on the data bus. This additional latency is optimized to reduce the number of idle time slots on the data bus when switching between a read instruction and a write instruction. Programmable registers are provided for adjusting the amount of latency.
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申请公布号 |
US6088774(A) |
申请公布日期 |
2000.07.11 |
申请号 |
US19970933673 |
申请日期 |
1997.09.19 |
申请人 |
ADVANCED MEMORY INTERNATIONAL, INC. |
发明人 |
GILLINGHAM, PETER BRUCE |
分类号 |
G06F13/42;G11C7/10;G11C7/22;(IPC1-7):G06F12/00 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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