| 摘要 |
PURPOSE: A semiconductor memory having a sub-word line driving circuit is provided to simplify a layout and to reduce the size of a memory chip by decreasing the number of additional NMOS(n-channel metal oxide semiconductor) transistors for connecting a sub-word line to a grounding. CONSTITUTION: A first sub-word line driving unit(200) has four sub-word line driving units(SWLD101-SWLD104) and first to third NMOS transistors. The first to fourth sub-word line driving units selectively output first and second lower pre-decoding signals(P0,P1) or grounding potentials to each sub-word line(SWL0,SW2,SW5,SW7) through inverted first and second global word line enable signals(GWLB0,GWLB1). Each first and second lower pre-decoding signal(PB0,PB1) inverted to a gate is fed and the same lower pre-decoding signals are transmitted to adjacent sub-word lines. The first to third NMOS transistors connect the adjacent sub-word lines.
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