| 摘要 |
<p>PROBLEM TO BE SOLVED: To speed up operation by providing a row address counter and giving a live-line state to a specified row in other bank before reading or writing is completed for the contents of the specified row in one bank. SOLUTION: The clock buffer 8 receives the basic clock, outputting to the command decoder 2, address buffer 6 and I/O buffer 16 through a signal line L1. The command decoder 2 accepts consecutive read and write command of a continuous row address and outputs to a mode register 4 through a signal line L2. The initial address is inputted in the address buffer 6, and inputted through a signal line L3 in a row address counter 10a, 10b and column address counter 12a, 12b, with the leading row and column addresses determined. By the row and column address counters 10b, 12b, the leading row and column addresses and all succeeding row and column addresses are consecutively read and written, making speed-up of operation possible.</p> |
