| 摘要 |
<p>PROBLEM TO BE SOLVED: To easily control the delay time of a variable delay buffer circuit into desired delay quantity by providing a counter for outputting a control signal for making the delay time coincident with prescribed time. SOLUTION: A frequency multiplying circuit 1 converts the frequency of an input clock to the prescribed multiple of frequency. A phase comparator 3 inputs the output clock of the frequency multiplying circuit 1 and the output clock of a variable delay buffer circuit 2 and outputs any one of UP signal and DOWN signal corresponding to the phase relation of two clocks. A counter 4 sends out a control signal CD0 for changing the delay time to the variable delay buffer circuit 2. The variable delay buffer circuit 2 selects any one of a route, to which plural unit delay gates are connected, and a route, to which no unit delay gate is connected. Finally, the delay time of the variable delay buffer circuit 2 is made equal to one cycle of output clock of the frequency multiplying circuit 1.</p> |
