发明名称 |
PLL CIRCUIT, PLL CIRCUIT CONTROLLER AND DISK DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit normally generating an output signal even when a noise is incorporated in a reference signal, and the pulse of the reference signal is lacked. SOLUTION: The PLL circuit 19 is provided with a period information generative circuit 37 and a control circuit 31. The period information generative circuit 37 generates a period information signal (k) of a prescribed period containing the period that the reference signal RC rises next is estimated by counting an output signal CLK. The control circuit 31 generates the next output signal CLK based on the reference signal RC when the reference signal rises in the prescribed period based on the period information signal (k), and inactivates a phase comparator 32 when the reference signal RC does not rise in the prescribed period to keep the generated output signal CLK.
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申请公布号 |
JP2000173194(A) |
申请公布日期 |
2000.06.23 |
申请号 |
JP19980351257 |
申请日期 |
1998.12.10 |
申请人 |
FUJITSU LTD;FUJITSU VLSI LTD |
发明人 |
NIWA TAKAHIRO;ITAKURA AKIHIRO |
分类号 |
G11B20/14;H03L7/08;H03L7/089;H03L7/14;H03L7/191 |
主分类号 |
G11B20/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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