发明名称 PROCESSOR AND INSTRUCTION PIPLINE PROCESSING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a processor which can shorten the processing time of a program. SOLUTION: When an instruction including a 1st indication for access to a 1st address on a data memory and a 2nd instruction for generation of a 2nd address from the 1st address and access to the 2nd address on the data memory 7 is executed through instruction pipeline processing, an ALU 55 generates the 2nd address by performing operation using the 1st address in the execution stage of the 1st indication and outputs the 2nd address to the data memory 7 in the execution stage of the 2nd indication and the data memory 7 accesses the 1st address in a memory access stage of the 1st indication and accesses the 2nd address in the memory access stage of the 2nd indication.
申请公布号 JP2000172502(A) 申请公布日期 2000.06.23
申请号 JP19980342099 申请日期 1998.12.01
申请人 SONY CORP 发明人 MIYOSHI TETSUO
分类号 G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/38
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