发明名称 |
DECODER AND DECODING METHOD |
摘要 |
The deterioration in the error characteristics at transition points in a transmission system is suppressed. A first adder calculates the SM value at a transition from state 00 to state 00 and produces output for a comparator. A second adder calculates the SM value at a transition from state 01 to state 00 and produces output for the comparator. The comparator compares such SM values, selects a maximum-likelihood pass, and sends the results to a set/reset register. An ACS controller detects the unique determination of transition of the state of fixed information (TAB1), outputs a reset signal to the set/reset register storing the SM value in the state to reset the resist value to 0, and outputs a set signal to the set/reset registers storing the SM values other than values corresponding to state 00 of the fixed information (TAB1) to set the resist value to the MAX value.
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申请公布号 |
WO0036756(A1) |
申请公布日期 |
2000.06.22 |
申请号 |
WO1999JP07007 |
申请日期 |
1999.12.14 |
申请人 |
SONY CORPORATION;IKEDA, TAMOTSU;MIYAUCHI, TOSHIYUKI |
发明人 |
IKEDA, TAMOTSU;MIYAUCHI, TOSHIYUKI |
分类号 |
H04L27/22;H03M1/00;H03M13/23;H03M13/41;H04B7/185;H04L27/00;(IPC1-7):H03M13/41 |
主分类号 |
H04L27/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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