发明名称 |
Semiconductor memory device implementing multi-bank configuration with reduced number of signal lines |
摘要 |
A memory cell array in a semiconductor memory device according to the present invention is divided into a plurality of banks along the row-direction. Each bank is further divided into a plurality of sub blocks along the column-direction. Sub blocks belonging to the same group, in other words, sub blocks arranged adjacent to each other along the row-direction share the same row address. An accessing operation to an addressed memory cell is performed on the basis of a sub block. The activation of a sub block is performed by a control circuit provided for each of the sub blocks based on a signal activated for each of the banks and the same group based on an address signal.
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申请公布号 |
US6078542(A) |
申请公布日期 |
2000.06.20 |
申请号 |
US19980204282 |
申请日期 |
1998.12.03 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TOMISHIMA, SHIGEKI |
分类号 |
G11C11/41;G11C8/12;G11C8/14;G11C11/401;G11C11/407;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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