| 摘要 |
PROBLEM TO BE SOLVED: To facilitate handling of the synchronizing clock signal of a semiconductor storage device. SOLUTION: A clock signal CLK is inputted to a timing control circuit 21 and a sense amplifier enable signal and concurrent bit line precharge signal SAET is held at high level, generated by a 1st delay circuit 102 and a 2nd delay circuit 106, after a trailing edge of the clock signal CLK, to generate the timing of activating a sense amplifier array 12, thereby obtaining a margin with which a couple of bit lines BL and /BL are charged. Furthermore, a row decoder enable signal RDENT and the sense amplifier enable signal and the bit line precharge signal SAET are held at low level, generated by a 4th delay circuit 110, after a rising edge of the clock signal CLK so as to obtain the timing of precharging the couple of bit lines BL and /BL.
|
