发明名称 |
Self-timed address decoder for register file and compare circuit of a multi-port CAM |
摘要 |
A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.
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申请公布号 |
US6072746(A) |
申请公布日期 |
2000.06.06 |
申请号 |
US19980134339 |
申请日期 |
1998.08.14 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DURHAM, CHRISTOPHER MCCALL;KLIM, PETER JUERGEN;WAITE, ROY KEITH |
分类号 |
G11C8/10;(IPC1-7):G11C8/00 |
主分类号 |
G11C8/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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