| 摘要 |
A semiconductor memory device having a sub-word line driving circuit overcoming disadvantages of a conventional semiconductor memory device having a sub-word line driving circuit in that it requires additional NMOS transistors with their gates applied with a predecoding signal in order to connect all sub-word lines to the ground which may be floated during the operation of the sub-word line driving circuit, and thus a layout of the device is complicated and a size of the memory chip is increased, can simplify the device layout and reduce the memory chip size by using the NMOS transistor connecting the adjacent sub-word lines which are applied with an identical predecoding signal but receive different inverted global word line enable signals.
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