发明名称 INPUT PROTECTION CIRCUIT AND OUTPUT BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain an input protection circuit and an output buffer circuit that give no effect on an operation or a characteristic of an integrated circuit device. SOLUTION: The input protection circuit 1 is configured such that an input signal line 11 connects to a drain of an NMOST Qn11, a gate of the NMOST Qn11 connects to a node V11 via a resistor R11 and a source of the NMOST Qn11 connects to a ground voltage source VSS. The node V11 connects to a constant voltage source whose level is lower than that of the ground voltage source VSS. When an external abnormal high voltage such as a surge is given to the input signal line 11 of the input protection circuit 1, the high voltage is applied also to the drain of the MNOST Qn11 to raise the voltage of the gate of the NMOST Qn11 and to cause a current flowing to the source of the NMOST Qn11 connecting to the ground voltage source VSS from the drain of the NMOST Qn11 thereby protecting the internal circuit to which the input signal line 11 connects.
申请公布号 JP2000134080(A) 申请公布日期 2000.05.12
申请号 JP19990295078 申请日期 1999.10.18
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRANO HIROSHIGE
分类号 H03K19/003;H03K19/0175;(IPC1-7):H03K19/003;H03K19/017 主分类号 H03K19/003
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