INTEGRATED CHIP DUMMY TRENCH PATTERN FACILITATING DEVELOPMENT OF TRENCH ETCHING PROCESS

摘要

PROBLEM TO BE SOLVED: To obviate the need for etching redesigning by laying out a deep trench pattern by using a dummy semiconductor material loading rate, that is obtained by subtracting a device trench level semiconductor material loading rate from an estimated final trench level semiconductor material loading rate. SOLUTION: First, a final chip design silicon loading rate is estimated, and a plurality of device deep trenche patterns are laid out, that constitute an integrated circuit chip 14 to be developed. These trenches cumulatively have device silicon loading rates. Next, the device silicon loading rate is subtracted from the the estimated final chip design loading rate so as to compute a dummy silicon loading rate, and cumulative silicon loading rates are used to lay out a plurality of dummy deep trenches 22. It is preferable have the device trenches disperse uniformly and the dummy trenches over a chip.