| 摘要 |
PROBLEM TO BE SOLVED: To distribute the load on a bus, to suppress the generation of response delay, and to greatly improve the reliability by providing a delay time storage means and a control means which inputs and outputs data while shifting the timing by a delay time according to the data transfer processing. SOLUTION: A CPU 101 is able to access the delay time storage means 3 by one of an I/O space, a memory space, and a PCI configuration space. Then, a value calculated by a software program in a memory 102 can be written to the delay time storage means 3. The delay time storage means 3 is a storage area mounted on a video interface 1 and connected to a control means 2. Then when the control means 2 transfers data to a PCI bus 102, the value stored in the storage area is read out and the start of the transfer is delayed by the time corresponding to the value to perform the data transfer.
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