| 摘要 |
<p>A ferroelectric integrated circuit memory (436) includes a memory cell (110) having a ferroelectric capacitor (112), one electrode (120) of which is connected to a bit line (130) through a transistor (114) and the other electrode (122) of which is connected to a plate line (132). The plate line is floating at one-half Vcc when the bit line is lowered to zero volts to develop a read voltage on the plate line. A unity gain amplifier (106) then drives a complementary plate line (131) to the same voltage as the plate line, then the plate line and complementary plate line are connected via a transistor (156), and the bit line is raised to Vcc to develop a reference voltage. This operation subtracts the read voltage from the reference voltage to develop a net voltage on the complementary plate line. The voltage on the complementary plate line is applied to an output line (158), compared via a sense amplifier (108) to a one-half Vcc voltage on an input line (157), and the sense amp then drives the input and output lines to zero and Vcc, depending on whether the developed voltage was greater or less than one-half Vcc.</p> |
