发明名称 |
Interrupt processing during iterative instruction execution |
摘要 |
<p>A processing engine comprises an instruction decode register adapted to buffer a complete instruction pending decode thereof, and a decode mechanism configured to decode instructions. The processing engine is responsive to a repeat instruction to repeat execution of a subsequent instruction and further responsive to an interrupt signal to interrupt said repeat execution of said subsequent instruction. <IMAGE></p> |
申请公布号 |
EP0992889(A1) |
申请公布日期 |
2000.04.12 |
申请号 |
EP19980402461 |
申请日期 |
1998.10.06 |
申请人 |
TEXAS INSTRUMENTS INC.;TEXAS INSTRUMENTS FRANCE |
发明人 |
PONSOT, ERIC;DJAFARIAN, KARIM;COUVRAT, MARC |
分类号 |
G06F9/32;G06F9/38;G06F9/48;(IPC1-7):G06F9/32 |
主分类号 |
G06F9/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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