MEMORY ADDRESS DECODING CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE

摘要

A decoding circuit (54) for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder (44), a lower bank decoder (58), an upper bank decoder (56), and a plurality of flexibly partitioned conductive lines connected between the upper and lower bank decoders (56 and 58). The flexibly partitioned conductive lines (60, 62, 64, ... 74) provide a plurality of bank address pre-decoding bits for the X-decoder (44) to row decode the memory cells along the respective word lines in the memory array (20). The memory array (20) includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are connected to two Y-decoders (32 and 34) which provide column decoding for the memory cells in the upper and lower memory banks.