发明名称
摘要 An integrated circuit (IC) fabricated on a semiconductor chip (51) is electrically connected through an array (50) of pads to leads (54) of a package; the pad array includes alternate long pads (50a) and short pads (50b) exposed by first openings (51e/51f) and second openings (51d), respectively, the openings having wide portions and narrow portions, and the wide portions of the first openings are offset from the wide portions of the adjacent second openings so that the manufacturer arranges the long pads and the short pads at a fine pitch less than 40 microns.
申请公布号 JP3022819(B2) 申请公布日期 2000.03.21
申请号 JP19970231523 申请日期 1997.08.27
申请人 发明人
分类号 H01L21/60;H01L21/822;H01L23/485;H01L27/04 主分类号 H01L21/60
代理机构 代理人
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