发明名称 |
Programmable logic array structure having reduced parasitic loading |
摘要 |
The present invention provides a PLA structure having logic interposed between an AND plane and an OR plane, wherein the interposed logic provides an additional set of minterms to the OR plane such that any PLA output function can be implemented with substantially fewer input signals. In this way, parasitic loading for implementation of any particular logic function is reduced.
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申请公布号 |
US6034543(A) |
申请公布日期 |
2000.03.07 |
申请号 |
US19970969009 |
申请日期 |
1997.11.12 |
申请人 |
INTEL CORPORATION |
发明人 |
HUANG, JIAN-HUI;PORTILLO, RALPH;GRUNER, FREDRICK R. |
分类号 |
H03K19/177;(IPC1-7):G06F7/38 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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