| 摘要 |
PROBLEM TO BE SOLVED: To shorten time disabling the transfer of data due to a retrial cycle and to prevent the reduction of transfer capacity. SOLUTION: In the case of executing a retrial cycle, an address, a byte enable signal and a command of a 1st read cycle started by a master device 1 are stored in an address/byte enable/command regitster 53 through a PCI interface 51 and data from a local bus device 9 are transferred to the master device 1 through a local bus interface 58, a data regiter 52 and a PCI bus interface 51. When a 2nd read cycle in which at least one of the address, the byte enable signal and the command is changed is started, the contents of the register 53 are destructed after the lapse of prescribed time and the contents are updated by at least one of the changed address, byte enable signal and command.
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