发明名称 Method and apparatus for testing compensated buffer circuits
摘要 A method and an apparatus for testing compensated input/output buffers. In one embodiment, a compensated input/output buffer includes a node from which a plurality of compensation devices are coupled in parallel to a particular voltage level, such as for example VCC or ground. Compensation control signals are received by each one of the compensation devices such that the compensation signals are configured to selectively switch on and off each one of the plurality of compensation devices. An input/output test bus is coupled to the node and thus has access to each one of the compensation devices. Test circuitry is configured to selectively switch on and off each one of the compensation devices such that a switchable conductive path is formed from the node to the particular potential level through each one of the plurality of compensation devices. By observing the switchable conductive paths through each respective compensation device from the input/output test bus, proper functionality of the compensation devices in the compensated input/output buffer is verified.
申请公布号 US6031385(A) 申请公布日期 2000.02.29
申请号 US19970823215 申请日期 1997.03.24
申请人 INTEL CORPORATION 发明人 ILKBAHAR, ALPER
分类号 G01R31/30;G01R31/317;(IPC1-7):G01R31/28 主分类号 G01R31/30
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