发明名称 Clock redundancy system
摘要 An information processing apparatus of the present invention is, in order to prevent a malfunction by an increase or a decrease of an oscillation frequency of a clock oscillator, provided with redundancy with 2n+1 (n is a positive integer) clock oscillators and includes a counter for counting a clock of each of the clock oscillators. Values of the counters are compared with each other at every certain timing to select a normal clock oscillator, and the clock of the oscillator is used by modules of the information processing apparatus. Accordingly, even if a little disorder in oscillation frequency occurs with any of the clock oscillators, the information processing apparatus continues to operate without stopping and without malfunctioning. Further, a difference between each two values is calculated, and an error is discriminated when the difference is higher than a certain value. By making it possible to freely set the value to be used for the discrimination of an error, it is possible to set a displacement in oscillation frequency of a clock oscillator which is to be discriminated as an error.
申请公布号 US6023771(A) 申请公布日期 2000.02.08
申请号 US19980113521 申请日期 1998.07.10
申请人 NEC CORPORATION 发明人 WATANABE, SHINJI
分类号 G06F1/04;G06F1/06;H03K3/02;H03K5/15;(IPC1-7):G06F1/06 主分类号 G06F1/04
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