| 摘要 |
PURPOSE: In a scan flip-flop circuit, after a logic value of a first input is latched in response to a first clock signal and a logic value of a second input is latched in response to a second clock signal, the two logic values are outputted for the second clock. CONSTITUTION: The scan flip-flop circuit (900) comprises: a serial input(902); a parallel input(904); a selective input(906); a control input(908); a first output(910); and a second output. When a test enable signal EN of the selective input and a control signal CNTL of the control input are all in a second logic state, the flip-flop circuit latches the test value of the serial input which outputs to the first output and the second output. When the test enable signal EN is set to the first logic state and the control signal CNTL remains in the second logic state, the flip-flop circuit latches the test value of the parallel input which outputs to the second output. Therefore the serial test value and the parallel test value respectively go to the first output and the second output at the same time.
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