发明名称 |
Synchronous clock generator including a compound delay-locked loop |
摘要 |
A synchronous clock generator is comprised of a delay-locked loop for producing a plurality of signals in response to an external clock signal. Each of the plurality of signals is delayed a predetermined period of time with respect to the external clock signal. A plurality of multiplexers is responsive to the plurality of signals for producing at least one clock signal in response to control signals input to the plurality of multiplexers. A clock driver is provided for driving the clock signal. A variable delay circuit is positioned to delay the external clock signal before input to the delay-locked loop. A compound feedback loop is responsive to certain of the plurality of signals for producing a control signal input to the variable delay circuit.
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申请公布号 |
US6011732(A) |
申请公布日期 |
2000.01.04 |
申请号 |
US19970915185 |
申请日期 |
1997.08.20 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
HARRISON, RONNIE M.;KEETH, BRENT |
分类号 |
G11C7/22;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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