| 摘要 |
A circuit is provided for controlling or regulating a phase-locked loop (PLL) output during times when the PLL is unlocked. Noise or corruption on the input signal of the PLL may cause the PLL output frequency to suddenly rise to match the input signal frequency. In many instances, the noise or corruption cannot be filtered by the low pass filter within the PLL. A detection circuit is coupled to receive the input signal, and discern times in which non-filterable noise occurs. The detection circuit may include a decoder which decodes, e.g., error correction coding within the input signal data stream to indicate possible instances in which the PLL will unlock. Once the detection circuit indicates an unlock condition and forwards an unlock selection signal to a multiplexer, the multiplexer chooses a frequency divided clocking signal rather than the PLL output clocking signal. The frequency divided clocking signal transitions at a rate acceptable to a digital processor, while the PLL output clocking signal during an unlock state is not acceptable. Thus, the digital processor can maintain its operating state during times when the PLL clocking signal exceeds the processor maximum operation frequency.
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