Process for depositing a stratified dielectric structure for enhancing the planarity of semiconductor electronic devices

摘要

A method of depositing a layered dielectric structure to improve the planarity of electronic devices which include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. The bit lines are isolated from one another by a layered dielectric structure to provide a planar architecture onto which an optional conductive layer may be deposited. The dielectric structure is formed from a highly planarizing dielectric layer of the SOG type spun over a first insulating dielectric layer and solidified by means of a thermal polymerization process. After solidifying the dielectric layer, it is subjected to a rapid thermal annealing treatment.