Semiconductor package with multilayer circuit, and semiconductor device

摘要

PCT No. PCT/JP96/03590 Sec. 371 Date Jul. 29, 1997 Sec. 102(e) Date Jul. 29, 1997 PCT Filed Dec. 6, 1996 PCT Pub. No. WO97/22146 PCT Pub. Date Jun. 19, 1997To provide a semiconductor package on which a multilayer circuit is formed by a so-called build-up system, capable of assuredly mounting a semiconductor chip and improving the reliability of a semiconductor device yield, and durability. The semiconductor package includes an insulating core substrate 10 on one surface of which is defined a semiconductor chip mounting area 20 for mounting the semiconductor chip 14. A circuit pattern 12 made of a metallic foil is also formed on this surface so that one end thereof extends into the semiconductor chip mounting area 20. Film-like circuit patterns 22 connected to the circuit pattern are formed in a multi-layered manner via a film-like insulating layer 18 around the semiconductor chip mounting area on the core substrate. By these film-like circuit patterns and the film-like insulating layer, the semiconductor chip mounting area 20 is defined as a recess.