摘要 |
<p>PROBLEM TO BE SOLVED: To realize setting of an operation mode without providing exclusive terminals for setting the operation mode and preventing ordinary operation during a normal operation of LSI. SOLUTION: An output of a tristate buffer 2 is wired to a data bus connecting between bidirectional terminals T1 of LSI1 and a memory 3. An output terminal T2 of LSI1 is connected to an output enable terminal of the tristate buffer 2. Responding to a mode signal fetching request signal S3 generated from a timer 22 in a constant time interval, a control means 21 generates a mode register timing signal S2, a fetching request enable signal S8 and output control signal of tristate buffer 2. Responding to the mode register timing signal S2, a mode register 10 inputs the setting data from a bidirectional buffer 40. Responding to the fetch signal S11 from a memory access judging means 23, the control means 21 sets the signals S2, S7, S8 in the waiting condition.</p> |