发明名称 Method for manufacturing a stacked electrode for a semiconductor device
摘要 A method for making a stacked gate electrode structure for a semiconductor device provides for three layers of the stacked structure including a first conductive layer, an insulating layer, and a second conductive layer. The layers of the stacked structure are to be of uniform width. The method includes forming on a gate oxide layer on the surface of the semiconductor substrate a first conductive layer, an insulating layer, and a second conductive layer in order. A photoresist is formed on the second conductive layer and patterning of the second conductive layer and the insulating layer using the photoresist as an etching mask is carried out. Side wall covering layers which result from the insulating layer patterning which cover the sides of both the second conductive layer and the insulating layer are removed. Thereafter, the first conductive layer is patterned using the photoresist as an etching mask.
申请公布号 US5928966(A) 申请公布日期 1999.07.27
申请号 US19970864067 申请日期 1997.05.28
申请人 SONY CORPORATION 发明人 YAMANE, TETSUYA
分类号 H01L21/28;H01L21/302;H01L21/3065;H01L21/318;H01L21/3213;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/312;H01L21/310;H01L21/283 主分类号 H01L21/28
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