Synchronous DRAM including an output data latch circuit being controlled by burst address

摘要

A synchronous DRAM for high-speed operation does not apply a burst address to a column address buffer under SDRAM's burst mode operation which receives only an initial address from an external part and produces a next address within a chip, but does reduce a signal path of the SDRAM by directly applying the burst address to a register storing the prefetched data, thereby enhancing operation speed. The SDRAM for high-speed operation includes: a mode register for programming a burst length; a column address buffer and latch means controlling an operation of the column decoder by a column active signal; a burst length counter means which generates a burst address as long as a programmed burst length to the mode register after receiving a burst start address; a burst control means for controlling the burst length counter means; and data latch means which temporarily stores the data transmitted to the global I/O line, and transmits the stored data to the data output buffer by controlling the burst address.