A METHOD OF MAKING A SELF-ALIGNED DISPOSABLE GATE ELECTRODE FOR ADVANCED CMOS DESIGN

摘要

A method of fabricating an integrated circuit transistor (10) in a substrate (20) is provided wherein a self-aligned gate electrode (30) is formed after the high temperature steps associated with sidewall spacer formation and source/drain anneal. A first dielectric layer (130) is formed on a substrate (20). First and second source/drain regions (50 and 60) are formed in the substrate (20) and spaced laterally to define a channel region (70) underlying the first dielectric layer (130). A second dielectric layer (150) is formed on the substrate (20) except where the first dielectric layer (130) is positioned. The first dielectric layer (130) is removed and a third dielectric layer (40) is formed that overlies the channel region (70). A gate electrode (30) is formed on the third dielectric layer (40). The first dielectric layer (130) functions as a disposable gate electrode to facilitate self-aligned source/drain implant and sidewall spacer formation.