发明名称 |
Mfr. technique for conducting elements within integrated circuit |
摘要 |
the deposition method enables formation of the conducting elements without need for polishing. The procedure for forming conducting elements within an integrated circuit comprises the stage of depositing a first dielectric layer (14) on a substrate (10). A first conducting layer (16) is then deposited upon this dielectric, and a second dielectric layer (18) is deposited on top of the conducting layer. Cavities (20) are formed, extending at least part way through the first dielectric layer. A second conductive layer is then formed on the internal surfaces of the cavities. Finally a further conducting material (26) is deposited electrolytically within the cavities.
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申请公布号 |
FR2773262(A1) |
申请公布日期 |
1999.07.02 |
申请号 |
FR19970016855 |
申请日期 |
1997.12.30 |
申请人 |
SGS THOMSON MICROELECTRONICS SA |
发明人 |
MOUSSAVI MEHDI;MORAND YVES |
分类号 |
H01L21/288;H01L21/768;(IPC1-7):H01L21/768 |
主分类号 |
H01L21/288 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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