| 摘要 |
PROBLEM TO BE SOLVED: To reduce a circuit scale without sacrificing operation accuracy and processing speed. SOLUTION: In a pre-processing, a divisor D and a dividend X are respectively supplied through selectors S1 and S2 to an adder-subtracter 33 and the selector 21 is selectively controlled based on the result. In a repetitive loop processing, kD/r and R(j) are supplied through the selectors S1 and S2 to the adder-subtracter 33. In a post-processing, the selector S1 is turned to a non- selection state, the output is turned to '0', the output of a quotient register R1 is supplied through the selector S2 and carry CRY=1 is supplied to the adder-subtracter 3. The judgement of round-up or round-down is performed by a rounding judgement part 43 parallelly to the operation, the selector S3 is made to select the output of the adder-subtracter 33 in the case of judging the round-up and the selector S3 is made to select the output of the quotient register R1 and the quotient register R2 is made to perform holding in the case of judging the round-down. |
