| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a synchronization circuit capable of synchronizing asynchronous signals of plural bits with the minimum delay. SOLUTION: This circuit is provided with a first synchronization circuit 1 for holding the respective bits of asynchronous signals composed of plural bits, a second synchronization circuit 2 for holding the asynchronous signals a fixed time after a period when the first synchronization circuit 1 holds the asynchronous signals, a matching detection circuit 3 for detecting whether or not all the corresponding bits of the respective output of the first synchronization circuit 1 and the second synchronization circuit 2 are equal, a selection circuit 4 for switching output signals by the detected result of the matching detection circuit 3, and a third synchronization circuit 5 for holding the output signals of the selection circuit 4 a fixed time after a period when the second synchronization circuit 2 holds the asynchronous signals. Since the selection circuit 4 switches signals to be outputted by the detected result of the matching detection circuit 3, output of synchronized signals is prevented from being delayed.</p> |
