| 摘要 |
<p>A memory cell (1) is provided with a MOS transistor (5) and a data holding capacitor (7). One of the two input-output electrodes of the transistor (5) is connected to a bit line (36) and the gate electrode of the transistor (5) is connected to a word line (37). The first electrode (6) of the capacitor (7) is connected to the other input-output electrode of the transistor (5), and the second electrode (14) is connected to a potential control circuit (40). When the data held in the memory cell (5) is HIGH, the potential control circuit (40) changes the potential at the second electrode (14) to a ground potential GND from a precharge potential VCC/2 after the write/read of the data held in the memory cell (1). When the data held in the memory cell (5) is LOW, the circuit (40) changes the potential at the second electrode (14) to a power supply potential VCC from the precharge potential VCC/2 after the write/read of the data.</p> |
