| 摘要 |
PROBLEM TO BE SOLVED: To enable a vertical field effect transistor with a U-shaped trench to be reduced in fluctuations for gate-cutoff voltage and protected against a withstand voltage fault due to short channel effects. SOLUTION: A vertical field effect transistor is equipped with an N<+> -type silicon substrate 1, an N-epitaxial layer 2, a P base region 5 formed by implanting P-type ions into the surface of the N-epitaxial layer 2, an N<+> source region 6 which is formed in the base region 5 and shallower than it, and a gate electrode 4 embedded in a trench through the intermediary of a gate oxide film 3 which covers the base and side of the trench. The base region 5 is highest in impurity concentration at a point 0.1μm or more deeper from its junction interface at the source region 6.
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