发明名称 |
Parasitic capacitance reduction for passive charge read out |
摘要 |
<p>A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground. <IMAGE></p> |
申请公布号 |
EP0915518(A2) |
申请公布日期 |
1999.05.12 |
申请号 |
EP19980308776 |
申请日期 |
1998.10.27 |
申请人 |
STMICROELECTRONICS, INC. |
发明人 |
GUERRIERI, ROBERTO;BISIO, MARCO;TARTAGNI, MARCO |
分类号 |
H01L27/146;G01B7/28;H04N5/357;H04N5/374;H04N5/378;(IPC1-7):H01L27/146;H04N3/15 |
主分类号 |
H01L27/146 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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