Load equalising adjustment circuit for trigger and power switch circuit low voltage (LV) installations
摘要
The circuit (1) includes a load equaliser which is fed by a current supply source (11) coupled to a full-wave rectifier (12) and a charge capacitor (CL). A load resistance (20) is connected in parallel with the capacitor. The load resistance is coupled to a switching transistor (21) and a resistance (24). A varying resistance voltage is supplied to a microprocessor (22). The voltage variations serve as a control signal which is utilised by the microprocessor for direct control of the transistor (21) in order to keep the current flow constant in the resistance. The processor supplies a clocked output signal to the transistor.
申请公布号
DE19749945(A1)
申请公布日期
1999.05.06
申请号
DE19971049945
申请日期
1997.11.03
申请人
SIEMENS AG, 80333 MUENCHEN, DE
发明人
ROEHL, WOLFGANG, DIPL.-ING., 13503 BERLIN, DE;BAUMGAERTL, ULRICH, 13599 BERLIN, DE