| 摘要 |
A microprocessor or microcontroller architecture which utilizes a 64 byte-register file in a unique manner. The lowest 16 bytes of the register file can be accessed as 16 8-bit registers (R0-R15), the lowest 32 bytes can also be accessed as 16 32-bit (word) registers (WR0-WR30), and the entire register file can be accessed as 16 64-bit (double word or Dword) registers (DR0-DR60). In this manner, various combinations of 8/16/32-bit registers are provided without wasting the register file. While providing at least 16 8/16/32-bit registers, only four bits are necessary to encode a register, thereby allowing two byte register-to-register instructions. The register file and an instruction sequencer operate to provide the 64 byte-register file which can be accessed so that the lowest 16 bytes of the register file are accessed as 16 8-bit registers (R0-R15), the lowest 32 are accessed as 16 word registers (WR0-WR30), and the entire register file is accessed as 16 double word registers (DR0-DR60).
|
