| 摘要 |
PROBLEM TO BE SOLVED: To provide a digital PLL circuit where a system operating by using an output clock surely and stably operates. SOLUTION: A phase comparison part 1 is provided with a comparator 3 detecting the rising phase difference of a reference clock and an output clock and outputting an up signal or a down signal when the detected phase difference becomes out of a prescribed permission range and an unlocking detector 4 outputting an unlocking signal showing that the phase of the output clock is in an unlocking state when the up signals or the down signals are continuously outputted twice. Since the phase synchronous state of the output clock with the reference clock is recognized in the system of a post-stage by the unlocking signal, the unlocking signal is changed from an L level to an H level and the system of the post-stage can be started. Then, the system operating by using the output clock can surely and stably operate. |
