发明名称 MULTIPLICATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a multiplication circuit which performs the multiplication of m/2 bits×n/2 bits parallelly for four sets and performs the multiplication of (m) bits×(n) bits as well without increasing the circuit area and operation time. SOLUTION: Multiplication circuits MA1, MB2, MA3 and MA4 respectively execute both the 16 bits×16 bits multiplication with codes and without codes. Selector circuits Sel1, Sel3, Sel5 and Sel7 for selecting the data of multiplicands and selector circuits Sel2, Sel4, Sel6 and Sel8 for selecting the data of multipliers are respectively added to the multiplication circuits MA 1, MA 2, MA 3 and MA 4. A connector circuit Con 1 connects an output out 16-3 from the multiplication circuit MA 3 and an output out 16-4 from the multiplication circuit MA 4 and an adder circuit Add 1 adds this connected value with data, for which an output out 16-1 from the multiplication circuit MA 1 and an output out 16-2 from the multiplication circuit MA 2 are shifted prescribed bits, and outputs the result.
申请公布号 JPH1195981(A) 申请公布日期 1999.04.09
申请号 JP19970253970 申请日期 1997.09.18
申请人 TOSHIBA CORP 发明人 YANO NAOYOSHI;TAMURA NAOYUKI
分类号 G06F9/38;G06F7/52;G06F7/527;G06F7/53;(IPC1-7):G06F7/52 主分类号 G06F9/38
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